A Hacker News thread discusses a claim in an article about RISC-V's rapid development outpacing Arm and x86. Commenters point out factual inaccuracies: the introduction date of RISC-V and historical advancements of x86. A major criticism is the article's focus on US companies, neglecting the significant contributions of Chinese RISC-V players like Alibaba, T-Head, and Espressif. The discussion then delves into the absence of a constant-time conditional move (CMOV) instruction in RISC-V, which is important for security-critical code to avoid timing side-channels. While a CMOV isn't currently part of the ratified standard, workarounds using bitwise operations exist. An extension named Zkt guarantees constant execution time for some instructions. There's debate on whether CMOV provides a significant performance boost on modern superscalar architectures, as well as the RISC-V standard itself makes no guarantees about execution time.