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原始链接: https://news.ycombinator.com/item?id=43851314

Hacker News 的讨论围绕着乐鑫 ESP32-C5 的量产发布展开,这款基于 RISC-V 架构的微控制器支持双频 Wi-Fi 6、蓝牙 5 和 Zigbee/Thread。用户们对 5GHz 支持和 Zigbee 集成(尤其用于电池供电设备)表示兴奋。一些人提到了 ESP32-C6 也支持 Zigbee,尽管价格略高。 人们也表达了对 ESP-IDF 的 BSD 系统易用性以及与 nRF 芯片相比的功耗的担忧。用户还讨论了缺乏对非引导协议设备的 USB Host HID 类驱动程序支持。开发套件的内存容量也得到澄清,为 384KB RAM 和 8MB Flash。 从 Xtensa 架构转向 RISC-V 的转变也引发了辩论,一些人强调 RISC-V 拥有更好的编译器支持和更低的授权成本,而另一些人则指出潜在的性能缺陷。一些人对 C5 的单核设计表示失望。AliExpress 上开发板的价格和供货情况也被提及。

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  • 原文
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    Espressif's ESP32-C5 Is Now in Mass Production (espressif.com)
    90 points by radeeyate 3 hours ago | hide | past | favorite | 57 comments










    Announced 2+ years ago (almost 3, now that I look: https://www.espressif.com/en/news/ESP32-C5 ) and sampling 1+ year ago, good to see it finally come. 5GHz support is increasingly important.


    Any guesses as to when a hobbyist might be able to buy the module without the dev board? Their aliexpress store didn't have them as far as I can tell, I assume they are prioritizing dev boards for the moment unless you're a big enough company to actually talk directly with Espressif.




    This is looking pretty great, I've really wanted a MCU with Zigbee on it, for the various little battery-operated devices I've wanted to make. However, with Espressif's lineup, I've really lost track of what does what, lately.

    Does anyone know of a good comparison resource?



    https://products.espressif.com/#/product-comparison

    This is a little bit more interactive and detail-oriented. I think they also have flashy onesheet PDFs that are more marketing oriented.



    The flashy PDF is here https://products.espressif.com/static/Espressif%20SoC%20Prod... a one-pager comparing all models.


    According to that pdf the ESP32-C5 does have Zigbee.


    The ESP32-C6 has a Zigbee radio. I have 6 myself -- they're great.


    I bought a few of those, but at $8 they're a bit pricier than the $3 Espressif spoiled me with.


    supermini boards with esp32c6 on it can be had for approximately 4 euro each.


    If anyone from Espressif seeing this, I love your MCUs. But can you please improve the ESP-IDF so that it's usable on BSD systems. The Linuxisms baked into its build system is unnecessary.

    I think moving from Make in the old version of IDF to CMake was a mistake.



    Love it or hate it, CMake is more or less the de facto build system for C/C++

    And just like any build system for everything language/stack, there is a small group of hardcore "enthusiasts" who create and push their true build tech to rule them all and then there is the large majority of people who have to deal with it and just want to build the damn thing.



    It should generally be easier to make a CMake buildsystem work well on the BSDs than hand-cobbled Makefiles, in terms of opportunities to introduce Linuxisms.


    I wonder if the power consumption is any better. An nRF runs circles around any existing ESP32 variants in terms of power.


    Not to mention the horrific peak power draw. It took people a while to figure out that the things need a fair bit of close-by capacitance on the power rail or they crash.


    How much capacitance? I built my own sensors based on ESP8266 and they've been flaky, and I wonder whether that's the issue.


    Coming out of deep sleep and Wifi coming back up, I’ve seen upwards of 600mA


    Wow, jeez, no wonder the USB won't power it...


    Let's hope they will finally enable the USB Host HID Class Driver to support non-boot protocol devices this go around.


    Any chance you could explain this to somebody who is just learning about HID and has run this example: https://github.com/espressif/esp-idf/tree/master/examples/pe... ? "non-boot protocol" I'm guessing is the key here? I don't have a super deep understanding of HID or what the "boot-protocol" refers to.


    The USB HID protocol is designed to support basically any device that regularly reports a set of values; those values can represent which keys are pressed, how a mouse has moved, how a joystick is positioned, etc. Now, different devices have different things that they support: joysticks have varying numbers of axes, mice have different sets of buttons, some keyboards have dials on them, etc. So, there's no single format for a report that simultaneously efficiently uses bandwidth and supports all the things a human interface device might do. To solve this, the HID protocol specifies that the host can request a "report descriptor" that specifies the format and meaning of the status reports. This is great for complex devices running a full OS; there's plenty of memory and processing power to handle those varying formats. However, these HID devices needed to also work in very limited environments: a real mode BIOS, microcontroller, etc. So, for certain classes of device such as keyboards and mice, there is a standard but limited report format called the "boot protocol". IIRC, the keyboard version has space to list 6 keys that are pressed simultaneously (plus modifiers), all of which must be from the same table of keys in the spec, and the mouse has an dX and dY field plus a bitfield for up to 8 buttons (four of which are the various ways you can scroll). To implement a more complex device, you'd want to be able to specify your own report format, which the ESP driver doesn't seem to allow you to do.


    I'll give you my anecdote. I'm building a device that reads the input of a USB game controller. In my case, it's a Sim Steering Wheel. I ended up needing to incorporate a MAX3421e USB Host chip to read the HID input, because the ESP firmware doesn't have this implemented. Hardware wise, all ESP32 chips with hardware USB could do this, but they haven't prioritized it in software. Some keyboards and Mice use a protocol called "boot protocol", and you can get those to work. It's not very common in game controllers though.


    how much memory does the dev kit have? it’s not clear after following links off that article.


    This image says 384 KB of RAM: https://docs.espressif.com/projects/esp-dev-kits/en/latest/e...

    It also says 320 KB of ROM, which seems low. Judging from the product name (DevKitC-1-N8R4) and their other products, it has 8 MB of flash.



    If it's like the other ESP32s with PSRAM support then 2-8MB most likely. IIRC it is addressed in the same way as the NAND, so the more RAM the less NAND you can have.

    Maybe not applicable for this new one, but that's my understanding for the S3/C5 models. (something like 16mb NAND and 8mb PSRAM)



    onboard memory is limited. PSRAM is available


    This microcontroller, like all microcontrollers Espressif released in the last few years, uses RISC-V as the ISA.


    I believe the C series is RISC-V, not the S series.


    Xtensa is a dead end, they said so on ESP32.com when someone pointed out the FPU ABI bottleneck


    I'm sure you're right. The current s3 chip is based on Xtensa, but it was released in 2020, so I guess the OP's statement is correct.


    Espressif made a decisive shift to RISC-V[0], effectively abandoning Tensilica.

    ESP32-S3 was, AIUI, their last non RISC-V chip.

    It was announced in 2020 and released in 2022.

    0. https://www.hackster.io/news/espressif-s-teo-swee-ann-confir...



    From the link

    >Espressif Systems (SSE: 688018.SH) announced ESP32-C5, the industry’s first RISC-V SoC that supports 2.4 GHz and 5 GHz dual-band Wi-Fi 6, along with Bluetooth 5 (LE) and IEEE 802.15.4 (Zigbee, Thread) connectivity. Today, we are glad to announce that ESP32-C5 is now in mass production.



    This wording is ambiguous- it's the first to support 5GHz, but it's not their first RISC-V core.


    Genuine question: is that a good or bad thing?


    It's a mix.

    Better compiler support for RISC-V, but everything I've seen from them is a much shorter pipeline than the older Xtensa cores, so flash cache misses hit it harder.

    Both RISC-V and Xtensa suffer from the lack of an ALU carry bit for the purposes of improving pipelining. But for these small cores it means 64-bit integer math usually takes a few more cycles than a Cortex-M Arm chip



    But that also depends on what you use it for. If you're after the wifi and IO and other nice things for a mostly idle device - the pipeline is almost irrelevant. Esphome can run on older versions just fine too. On the other hand if you're doing something very optimised and need tight timing around interrupts to drive external hardware - it may matter a lot.

    So... depends on the project.



    The Xtensa variants also come with dual core options, which means you can offload timing sensitive stuff to a dedicated core.

    My playing with C3 betrayed that you have to use much larger buffers for things like i2s to make it work without glitching.



    Absolutely correct.


    It's a big plus if you want to write code for it in something like Rust. LLVM support for the architecture they used on their older chips (xtensa) for a very long time required compiling a fork of LLVM and rustc in order to target the chips. It may still, I didn't keep up with the effort to upstream that target. RISC-V is an open architecture that has a lot of people excited so compiler support for it is very good. Though as far as why Espressif is using it, it feels likely they would use it because it means they don't have to pay anyone any royalties for the ISA.


    Unless you're a shareholder of arm, hard to see how it's a bad thing.


    The other core they've used is Xtensa


    Does it have floating point hardware?

    Does it have CAN?

    How does the core compare to their old ones?

    I'm a little disappointed that it only has one core even though I haven't used the second one on the older chips yet.





    They link to a $15 developer board on Aliexpress (much the same as the rest of the ESP developer boards floating around for years) which is now inflated to $35 with tax, shipping, and tariff.

    My impulse purchase has been tempered with "eh, do I really need it?"



    Even $15 is on the high end for Espressif dev boards. Not that it's saying much.

    If all you need is Zigbee/BLE and a few IO pins, an nRF52840 dongle is still $10 on DigiKey.



    These are ones actually made by Espressif and limit is one per person (presumably supply issues as they ramp up mass production), certainly there will be dozens of clones soon.


    Fortunately it’s only £16.40 with VAT and shipping to the UK. Approx $21.85. Comparable to the £9 M5Stack AtomS3 Lite (ESP32-S3) I picked up from Pi Hut recently.


    This should help all the US-based RISC-V microcontroller companies though, right? /s


    Finally all the mom and pop chip fabs running out of a garage get a fighting chance.


    Can't wait to buy from some west coast hipster with a garage fab now that it's economically viable. /s


    The really criminal thing is it only costs $8.43 to mail that thing from China to your house in the USA... it likely would cost you more to mail that same item to yourself from yourself.

    That alone puts US-based sellers at a mega disadvantage compared to cheap Chinese goods - and it's not a good thing.



    Most of my Aliexpress electronics orders are shipped to a local US Aliexpress distribution center which then mails them locally. These come in small padded envelopes which are not expensive to ship.


    >The really criminal thing is it only costs $8.43 to mail that thing from China to your house in the USA... it likely would cost you more to mail that same item to yourself from yourself.

    These things are tiny and very cheap to ship. I could probably pack 40 of them into a USPS flat rate box shipped anywhere in the US for $9.30.

    This was a decent argument when you could get things shipped from China for $0.50, but not now or in this case.



    $126/ea in quantity after tariffs.

    Why do I have this sickening feeling that in a few years anyone doing anything with hardware is going to be ordering everything direct from China?



    from my understanding RISC-V chips are slower and more expensive and less optimized compilers, so why in the world would an end user use one?


    No? Performance is implementation specific, they’re usually cheaper than ARM since there’s no core ISA license overhead, and while the core instruction set being extremely limited does cause a little bit of tension in compiler land, most cores with a baseline set of extensions get reasonable code generation these days.

    One of the main reasons RISC-V is gaining popularity is that companies can implement their own cores (or buy cheaper IP cores than from ARM) and take advantage of existing optimizing compilers. Espressif are actually a perfect example; the core they used before (Xtensa) was esoteric and poorly supported and switching to RISC-V gives them better toolchain support right out of the gate.



    But where do the original Xtensa cores place then?






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