Web-based IBM 1620 emulator and IPL-V from 1963

原始链接: https://github.com/pkimpel/retro-1620

该项目提供了一个 IBM 1620 Model 2 的网页版模拟器。IBM 1620 是一款于 1962 年推出的晶体管化、十进制、变长字段计算机。1620 系列专为科学与工程应用设计，采用了独特的内存到内存架构，没有软件可访问的寄存器。 Model 2 是对 1959 年原始 Model 1 的重大升级，提供了更快的周期时间、标准的硬件除法以及可选的索引寄存器支持。该系统使用磁芯存储器，数据按位进行顺序处理，算术运算（如乘法）依赖于驻留在内存中的查找表。 1620 支持多种外围设备，包括读卡器、磁盘驱动器和绘图仪，甚至还被用于过程控制配置。编程主要通过 SPS 汇编语言和 FORTRAN II 进行，配备磁盘的系统还可使用“监视器”（Monitor）系统。当前项目旨在通过网页浏览器模拟 Model 2，并保护和恢复该时代的原始软件。本项目采用 MIT 许可证发布。

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原文

Web-based emulator and operating environment for the IBM 1620 Model-2 computer system.

The IBM 1620 was a 1960s transistorized, decimal, variable field-length, magnetic-core memory computer system designed primarily as an inexpensive solution for scientific and engineering applications. There were two models, the original Model 1 released in 1959, and the object-code compatible but significantly redesigned Model 2, released in 1962. A total of about 2,000 systems were produced, roughly half each Model-1s and Model-2s. IBM supported the system until 1970.

The 1620 used a two-address, memory-to-memory architecture. There were no software-accessible registers. Instructions were a fixed 12 digits, consisting of an operation code of two digits, a "P" address of five digits (usually the destination operand), and a "Q" address or literal value of five digits (usually the source operand). The basic memory size was 20,000 digits, expandable to 60,000 digits. Each digit contained a four-bit binary-coded decimal value, a fifth "flag" bit used for both the arithmetic sign and as a field delimiter, and an odd-parity "check" bit. All arithmetic and data movement was done digit-sequentially.

The Model 1 featured a memory cycle time of 20µs per two digits. Addition and multiplication were done via a lookup table in memory. Hardware division, floating-point arithmetic, and indirect addressing were optional features.
The Model 2 featured a memory cycle time of 10µs per two digits. Many instructions were optimized to process two Q-operand digits from a single memory fetch. Addition was done in hardware, but multiplication was still done by table lookup. Hardware division and indirect addressing were standard features, with floating-point still an extra-cost option. The Model 2 had two additional options, index register address modification (with the index registers stored in memory at 00300-00399, where the Model 1 add table had resided) and support for binary (actually, octal) bit-wise operations, octal/decimal conversion, and binary paper tape I/O.

Initially, the Model 1 supported only paper-tape and typewriter input/output devices, but the 1622 card reader/punch unit (derived from the IBM 1401's model 1402 reader/punch) was made available soon after the initial release. Additional peripherals were the 1443 line printer, 1311 disk drive with removable disk packs, and 1627 plotter. The typewriter, paper tape, punched card, and printer devices supported alphanumeric data in memory as pairs of adjacent digits.

The 1620 was also used as the computing and control component of the IBM 1710 and 1720 process-control systems. When configured for this role, the 1620 supported several additional instructions and a multi-level interrupt system.

The 1620 had a vast collection of IBM-supplied and user-written software. Most programming was done using the SPS assembler or FORTRAN II. For systems with the 1311 disk drive, there was a simple batch operating system known as "Monitor."

The main goals of this project are creation of a web browser-based emulator for the Model 2 variant of the system and recovery of as much software for the system as we are able to find.

The contents of this project are licensed under the MIT License.