AMD Ryzen 是如何在两年内实现性能提升 50% 的?
How did AMD Ryzen get 50% faster in two years?

原始链接: https://lemire.me/blog/2026/09/18/how-did-amd-ryzen-get-50-faster-in-two-years/

与CPU技术停滞不前的观点相反,AMD的Ryzen 7 “X3D”系列展示了显著且持续的性能增长。对比Zen 3 (5800X3D)、Zen 4 (7800X3D) 和 Zen 5 (9800X3D) 处理器,2022年至2024年间,其单核性能提升了47%,多核性能提升了58%。 这些增长并非仅靠时钟频率驱动,时钟频率仅有15%的适度增长。相反,AMD通过增加50%的晶体管数量使核心显著“变宽”来实现这些成果。关键的架构改进包括更高的发射宽度(从每周期6条指令增加到8条)、更大的缓存容量、更多的整数算术逻辑单元(ALU),以及更大的重排序缓冲区以更好地管理指令流。此外,Zen 5通过将SIMD单元加倍至512位宽度,标志着数据并行处理的重大转变。随着业界展望Zen 6,这些桌面芯片的演进证明了CPU创新依然充满活力且激进。

这篇 Hacker News 讨论探讨了过去两年 AMD Ryzen 性能迅速提升背后的驱动因素。用户将其归功于以下几项技术改进: * **散热与设计效率:** X3D 芯片缓存位置的调整改善了散热,从而实现了更高的时钟频率并减少了过热降频。 * **制造工艺:** 更先进的制程节点降低了电压需求,使其能在相同的热设计功耗内实现更高频率。 * **架构:** 评论者指出,Ryzen 的可扩展性远超 AMD 此前的 FX 系列,并将其与英特尔 Nehalem 架构的影响力相提并论。 * **软件优化:** 除了硬件层面,用户强调 Linux 内核更新、开源编译器 (GCC) 的持续改进以及 x86-64v3 指令集目标对性能提升贡献巨大。 * **战略发布节奏:** 一些观点认为,50% 的增长数据受到了 3D V-Cache 版本发布时间的影响,这可能会放大年度增长幅度。 总体而言,社区对 Zen 6 等未来迭代产品持乐观态度,同时指出像 9950X3D 这样的现有芯片在处理高负载任务时仍极具竞争力。
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原文

People still tell me that CPUs are boring. That nothing much happens anymore.

Let us look at AMD Ryzen 7 processors from 2022 to 2024: the 5800X3D (Zen 3), the 7800X3D (Zen 4) and the 9800X3D (Zen 5). They are comparable 8-core chips with 3D V-Cache. I have written about them before, in How stagnant is CPU technology?

On Geekbench 6, performance went up by about 50% in two years.

Geekbench 6 single-core and multi-core scores for Ryzen 7 5800X3D, 7800X3D and 9800X3D

2022
5800X3D
Zen 3
2023
7800X3D
Zen 4
2024
9800X3D
Zen 5
Single-core 2,016 2,426 2,969
Multi-core 11,832 15,508 18,751

The 2024 chip is 47% faster on a single core than the 2022 chip, and 58% faster with all cores.

The clock did not do that. Max boost went from 4.5 GHz to 5.2 GHz, a 15% increase.

Base and max boost frequencies for Ryzen 7 5800X3D, 7800X3D and 9800X3D

2022
Zen 3
2023
Zen 4
2024
Zen 5
Base 3.4 GHz 4.2 GHz 4.7 GHz
Max boost 4.5 GHz 5.0 GHz 5.2 GHz

The number of transistors is way up, by about 50%, from roughly 11 billion to 16 billion. Most of the extra transistors went into the core, not the cache.

Transistor counts for Ryzen 7 5800X3D, 7800X3D and 9800X3D, split into core, I/O and cache

How do you turn extra transistors into extra performance?

You make the core wider, and you give it more to work with. Dispatch width went from a maximum of 6 instructions per cycle to 8. The L2 cache per core doubled, from 512 KB to 1 MB. The L1 data cache went from 32 KB to 48 KB. Integer ALUs went from 4 to 6. The reorder buffer grew from 256 to 448 entries, so the processor can keep more instructions in flight and schedule them better.

Cache sizes, dispatch width, integer ALUs and reorder buffer from Zen 3 to Zen 5

Zen 3
2022
Zen 4
2023
Zen 5
2024
L2 cache per core 512 KB 1 MB 1 MB
L1 data cache 32 KB 32 KB 48 KB
Dispatch width 6 6 8
Integer ALUs 4 4 6
Reorder buffer 256 320 448

For data parallelism (SIMD), Zen 5 is a different machine. Zen 3 and Zen 4 had four 256-bit SIMD arithmetic units. Zen 5 has four 512-bit units. Loads and stores widened the same way: two 512-bit loads per cycle, one 512-bit store.

SIMD arithmetic units, loads per cycle and stores per cycle from Zen 3 to Zen 5

Zen 3
2022
Zen 4
2023
Zen 5
2024
SIMD arithmetic units 4 × 256-bit 4 × 256-bit 4 × 512-bit
Loads per cycle 2 × 256-bit 2 × 256-bit 2 × 512-bit
Stores per cycle 1 × 256-bit 1 × 256-bit 1 × 512-bit

I already made the point that processors are getting wider. This is what that looks like on a desktop chip you can buy.

What about the next step? Zen 6 is arriving. AMD is talking about a 256-core Epyc part (Venice) with a gigabyte of L3 cache. We do not yet know what the desktop cores will look like. It could be wild.

Further reading: AMD’s 256-core Epyc 9996 ‘Venice’ (Tom’s Hardware).

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