Samsung Electronics unveiled next-generation 3D memory technologies, including z-axis High Bandwidth Memory (zHBM) and zNAND-O, as the company seeks to strengthen its position in the rapidly growing artificial intelligence market.
Samsung on Aug. 5 showcased mockups of zHBM and zNAND-O for the first time at the Future of Memory and Storage (FMS) 2026 conference in California. During a keynote presentation on Aug. 4 local time, the company also outlined its vision for maximizing performance and power efficiency in high-performance computing (HPC) and AI systems through the use of zHBM, zNAND-O and other advanced memory technologies.
zHBM Delivers Up to Eight Times Higher Performance Through New Architecture
zHBM is a next-generation architecture that vertically stacks HBM on top of AI accelerators, or xPUs, along the z-axis. The design minimizes the distance data must travel between memory and AI processors, improving bandwidth and power efficiency while supporting the ultra-high-speed data processing required for training and inference of large-scale AI models.
Conventional architectures place HBM around the AI accelerator. Samsung said that approach faces limitations in meeting the performance requirements of next-generation HPC and AI infrastructure.
According to the company, zHBM can deliver up to eight times the data-processing performance of eighth-generation High Bandwidth Memory (HBM5) while improving performance per watt by a factor of three. Thermal resistance is reduced by more than half, enhancing both system stability and energy efficiency.
Samsung described zHBM as a customizable family of 3D memory products. The architecture allows customers to add semiconductor intellectual property (IP) blocks to an interlayer positioned between the memory and AI accelerator. These blocks can be tailored to expand memory capacity or optimize accelerator performance for specific workloads.
The company said it plans to work closely with customers to co-optimize AI processors and memory systems and maximize the performance potential of zHBM.
Samsung Reveals HBM-Like zNAND-O and 400-Plus-Layer V10 BV-NAND
Samsung also introduced zNAND-O, a next-generation high-performance NAND flash family currently under development. The technology combines Samsung's vertical V-NAND stacking architecture with Through-Silicon Via (TSV) technology. TSVs are used in HBM to electrically and physically connect vertically stacked DRAM dies. Samsung's zNAND-O adopts a structure similar to High Bandwidth Flash (HBF), which is being developed by SK Hynix and Sandisk.
The "O" in zNAND-O refers to on-device AI applications. Samsung demonstrated four-layer and eight-layer 3D-packaged V-NAND configurations designed to deliver high space efficiency, increased read bandwidth and faster response times. The company said the technology is well suited for environments requiring real-time processing of large volumes of data.
During the keynote, Samsung also unveiled its V10 Bonding Vertical (BV)-NAND technology featuring more than 400 layers. The next-generation NAND architecture improves both performance and power efficiency. The displayed zNAND-O mockup was built using the V10 NAND platform.
BV-NAND separates the NAND cell array and peripheral circuitry onto different wafers before vertically bonding them together. The process utilizes advanced wafer-bonding technology that enables three-dimensional integration of multiple wafers.
Samsung further combines the approach with a three-stack architecture, in which V-NAND cells are manufactured in three separate stacks and then vertically interconnected. The company said memory density improves by approximately 58% compared with the previous V9 generation, enabling greater storage capacity within the same footprint. Read, write and input/output performance have also been enhanced.
HBM4E, HBM5 and Processing-in-Memory Technologies Also Displayed
Samsung's exhibition area featured more than 30 memory products spanning DRAM and NAND technologies. Highlights included a next-generation AI computing platform based on HBM4E, wafer samples, and an HBM5 mockup incorporating Heat Path Block (HPB) technology. HPB adds vertical heat-dissipation channels along the sides of HBM core dies to improve thermal management.
The company also showcased LPDDR5X-PIM, which combines low-power LPDDR5X DRAM with Processing-in-Memory (PIM) functionality. Samsung described the product as the world's first implementation of its kind, enabling more efficient data movement and improved power efficiency.
Storage products optimized for AI workloads were also displayed, including the PM1763 and BM1773. PM1763 is Samsung's next-generation enterprise solid-state drive (SSD), designed for high-speed reading and efficient data processing. BM1773 is an ultra-high-capacity enterprise SSD aimed at supporting large-scale AI training datasets.
Samsung emphasized that it remains the world's only integrated device manufacturer (IDM) capable of providing a one-stop solution spanning memory, logic semiconductors, foundry services and packaging.
"We can provide integrated services from the product design stage through mass production, helping customers shorten development cycles while optimizing performance and power efficiency," the company said. "This enables customized AI semiconductor solutions tailored to customer requirements."